公司创业初期,已获得知名投资机构的战略投资,公司坐落于上海浦东新区张江高科技园区内,欢迎希望致力于该技术领域的各类人才加入公司。公司将为员工提供良好的福利待遇和各类培训。 主要福利可能包括:

- 五险一金

- 补充公积金

- 午餐、交通津贴

- 员工补充医疗保险、双子女医疗保险

- 股权激励计划

- 全面健康管理、健身活动


欢迎有意者将简历发送至 recruitment@vastaitech.com,并请将所投职位包含于邮件标题中。

招聘信息

北京地区 上海地区
[PD] 芯片后端设计工程师 – PR [PD] 芯片后端设计工程师 IR/EM 客户解决方案架构师 [SW] AI编译器架构师 [SW] DSP软件开发工程师 [SW] MCU 固件开发工程师 [SW] 软件工具开发工程师 [SW] 视频编解码软件工程师 [SW] 深度学习算法工程师 [SW] 深度学习推理框架软件工程师 [PD] (资深)物理设计工程师 [FE] SOC flow Engineer [FE] SOC Low Power Design Engineer [FE] Staff STA Engineer

[PD] 芯片后端设计工程师 – PR 

岗位职责:

1.    模块级的netlistGDS的后端物理实现,包括floorplan,  placement, CTS , routing

2.    解决模块 timing, congestion, 以及IR/EM等问题

3.    负责模块的时序收敛及signoff工作

4.    负责模块的物理验证工作,包含DRCANTLVSERCIREMESD

任职要求:

1.    本科及以上学历,电子工程,微电子,计算机,通信等相关专业;

2.    三年以上芯片后端实现相关工作经验;

3.    熟悉半导体基本知识、原理,以及数字后端的基本知识;

4.    熟练使用ICC/Innovus/PT/StarRC/CalibreEDA工具;

5.    熟练使用TclPerlshell等脚本语言;

6.    有16nm及以下项目经验者优先;

[PD] 芯片后端设计工程师 - IR/EM

岗位职责:

1.    负责芯片的IR Drop分析以及优化

2.    负责芯片powersignal EM分析以及提高

3.    负责blocktop levelpower规划


任职要求:

1.    本科及以上学历,电子工程,微电子,计算机,通信等相关专业;

2.    三年以上芯片后端实现相关工作经验;

3.    熟悉半导体基本知识、原理,以及数字后端的基本知识;

4.    熟练使用Redhawk, voltus, ICC2, InnovusEDA工具;

5.    熟练使用TclPerlshell等脚本语言;

客户解决方案架构师 

Customer Solution Architect


职责描述 Responsibilities

作为瀚博半导体的客户解决方案架构师(SA),您将负责发展与云数据中心客户的深度技术合作,设计最优解决方案,力助客户赢得业务成功。职责包含但不限于:

1.    深入理解客户业务需求,推动跨部门合作优化关键系统设计,解决客户应用场景的痛点;

2.    提供完整的售前技术支持,确保客户成功评估并部署瀚博半导体产品,完成项目交付;

3.    结合项目经验、客户诉求与行业趋势,协助下一代产品定义,完善行业解决方案,扩大客户群体。

任职要求 Qualifications

1.    本科或以上学历,计算机、电子、通信等相关专业;

2.    5年以上电子或软件技术解决方案、售前或产品研发工作经验;

3.    良好的口头与书面技术沟通能力和团队协作精神,能独立面向客户沟通需求与解决方案;

4.    善于设计与搭建软硬件概念原型(Proof-of-Concepts),能独立完成客户演示;

5.    具备客户现场样品调试和编程解决问题的经验;

6.    熟悉半导体芯片(GPU, FPGA, ASIC)、深度学习框架与模型、计算机视觉或视频编解码技术者优先考虑;

7.    了解云架构、服务器硬件与软件,了解性能优化相关技术者优先考虑;

8.    熟悉人工智能、大数据、互联网等行业客户的应用场景和客户痛点者优先考虑;

9.    具备复杂项目管理经验者优先考虑。

[SW] AI编译器架构师


Job description:

1. 与IP/SOC设计团队合作进行自研AI芯片的SW/FW/HW协同设计及验证;

2. 对自研AI芯片编程模型进行抽象以便于软件开发。


Minimum Requirements:

1. 熟悉C/C++;

2. 熟悉CUDA/OpenCL者尤佳;

3. 熟悉计算机系统体系结构者尤佳;

4. 熟悉主流深度学习网络模型者尤佳;

5. 熟悉XLA/TVM/Glow/OpenVINO/TensorRT等AI编译器者尤佳;

6. 熟悉LLVM/GCC等编译器者尤佳。

[SW] DSP软件开发工程师


Job description:

1、  DSP 固件开发;

2、  DSP 视觉算法软件开发;

3、  DSP 软件指令、算法优化;

4、  为客户研发提供底层软件支持。

Minimum Requirements:

1、  计算机、电子、通信等专业本科及以上学历;

2、  3年以上DSP软件开发经验,至少对一种DSP 硬件架构、运行机制理解深刻;

3、  具有很强的C/C++编程能力,具备DSP汇编语言编程能力;

4、  具有AI 芯片软件开发经验、各种AI网络常用算子实现的工作经验尤佳;

5、  有半导体公司核心BSP开发团队工作经验者尤佳。

[SW] MCU 固件开发工程师


职位描述:

负责以下一项或全部工作:

1、  MCU 固件开发;

2、  基于芯片bare metal环境下的功能验证开发及调试;

3、  芯片IP驱动开发;

4、  为客户研发提供底层软件支持。

职位要求:

1、  计算机、电子、通信等专业本科及以上学历;

2、  对MCU 硬件架构理解深刻、具备bare metal驱动开发经验;

3、  具有很强的C/C++编程能力,具备一定的汇编语言编程能力;

4、  具有AI 芯片软件开发经验、各种AI网络常用算子实现的工作经验尤佳;

5、  有半导体公司核心BSP开发团队工作经验者尤佳;

6、  有DDR、PCIE、ethernet、SD、video codec、power 其中一种或多种驱动开发经验者尤佳

[SW] 软件工具开发工程师


岗位职责:

1. 开发AI加速器芯片的各主要模块的tracer/profiler/debugger

2. 开发AI加速器芯片SDK/IDE

3. 对AI加速器芯片进行性能/能效分析和优化


任职资格:

1. 掌握应用程序开发技术

2. 掌握至少一种应用程序开发语言(C/C++/Python/Java/C#)

3. 有较强的分析问题和解决问题的能力,具备较强的沟通能力和独立工作能力

[SW] 视频编解码软件工程师


Job description:

-H264/HEVC等视频编码器的驱动及中间层软件;

-编写与所开发代码配套的流程图,设计文档等;


Minimum Requirements:

-熟悉C/C++编程

-熟悉Linux环境下驱动开发

-对视频编解码的原理和码流格式有一定了解;

-有视频相关的驱动/中间件/应用层代码编写/调试经验

[SW] 深度学习算法工程师


Job description:

研究/分析主流AI模型特点,协助软件和硬件设计;

使用tensorflow/pytorch/mxnet/caffe之一实现/复现主流AI模型。


Minimum Requirements:

1、熟悉C/C++;

2、熟悉Python;

3、熟悉CUDA者尤佳;

4、熟悉AI算子实现者尤佳。

[SW] 深度学习推理框架软件工程师


职责描述:
-针对深度学习推理的编程框架的设计与实现;
-编写与所开发代码配套的流程图,设计文档等;


任职要求:
-熟悉C/C++编程
-熟悉Linux环境下软件开发
-对主流CNN/RNN/BERT等有一定了解;
-有深度学习系统的部署经验;

[PD] (资深)物理设计工程师

Staff Physical Design Engineer


Job description:

Work with Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron AI chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.

Minimum Requirements:

1. MSEE with 5+ years or Bachelor with 7+ years of industrial experience in ASIC design

2. 5+ years or more years of experience in physical design of deep submicron digital ASIC chips

3. Hands on experience in large scale ASIC chip physical design

4. Knowledgeable in all aspects of deep submicron ASIC design flow

5. Successfully gone through several complete product development cycles

6. Demonstrate strong leadership and work well with cross-functional teams

7. Good listening, writing and speaking English

8. Good communication skills, strong interpersonal skills and the flexibility

9. Dedicated, hard working and good team player

10. Familiar with Back-End (physical design) EDA tools

11. Familiar with Front-End EDA tools is a plus

12. Familiar with Unix/Linux environment and good at scripts

Senior Staff SOC flow Engineer


Responsibilities

1. Develop and maintain methodology and flows related to Synthesis/Timing Analysis/Formality Check/Lint/CDC etc.

2. Resolve flow and EDA tool issues to support project execution.

3. Integrate and validate new EDA tools in the flows.

4. Participate in SoC/IP level synthesis/ timing analysis / formality check / CDC check etc.


Requirements

1.      MSEE with > 7year+ experience of digital design experience;

2.      Should have proficiency in flow development and scripting.

3.      Be proficient at scripts language like TCL / Perl / shell / Python / makefile or others

4.      Familiar with EDA tools such as DC/Formality/primetime/spyglass etc.

5.      Must have good communication and analytical thinking skills.

6.      Proficient in English language and application


Professional Skills

1.      Excellent communication and organizational skills

2.      High level of analytical thinking

3.      Quality and risk management skills


Special Requirements:

1.      Customer Orientation, People Orientation, Achievement Orientation

2.      Leadership, Impact and Self confidence

Senior Staff SOC Low Power Design Engineer


Job Objective: SOC power estimation and optimization


Responsibility

1. Work closely with software, hardware and IP team to plan the chip clock architecture and low power proposal

2. Power estimation and optimization before chip TO, power breakdown and analysis after chip back

3. Low power features development and verification

4. Co-work with design and verification teams on power test plan

5. Define power optimization solution/methodology/flow and drive them into the design


Requirements

1.      MS with 5+ years' or BS with 8+ years' experience in ASIC design

2.      Experienced in power analysis and optimization

3.      Experienced in low power design

4.      Experience with power tools PowerArtist, PowePro, PTPX

5.      Familiar with scripting languages like Perl, Python, Makefile, etc

6.      Good understanding of the synthesis and backend flows

7.      Strong problem solving, teamwork and communication skills

8.      Proficient in English language and application


Professional Skills:

1.      Excellent communication and organizational skills

2.      High level of analytical thinking

3.      Quality and risk management skills


Special Requirements:

1.      Customer Orientation, People Orientation, Achievement Orientation

2.      Leadership, Impact and Self confidence

[FE] Staff STA Engineer

Responsibilities

1. Block and full-chip level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation).

2. Develop and maintain methodology and flows related to timing verification and closure.

3. Generate block and full chip level timing constraints.

4. Resolve complex timing issues for major building blocks of complex SoCs.

 

Requirements

1. 3/5+ years' experience in ASIC timing constraint generation and timing closure.

2. Thorough knowledge of the ASIC design timing closure flow and methodology.

3. Experience in STA tools and flows.

4. Knowledge of timing corners/modes, process variations and signal integrity related issues.

5. Hands on experience in timing/SDC constraints generation and management.

6. Proficient in scripting languages (TCL and Perl)

7. Strong ability in constraint analysis and debug, using industry standard tools such as Synopsys GCA

8. Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and bist testing

9. Proficient in English language and application

 

Professional Skills

• Excellent communication and organizational skills                                        

• High level of analytical thinking                                     

• Quality and risk management skills                                       

 

Special Requirements:

• Customer Orientation, People Orientation, Achievement Orientation

• Leadership, Impact and Self confidence

[PD] 芯片后端设计工程师 – PR [PD] 芯片后端设计工程师 IR/EM 产品市场专员 客户解决方案架构师 [SW] AI编译器架构师 [SW] DSP软件开发工程师 [SW] MCU 固件开发工程师 [SW] 软件工具开发工程师 [SW] 视频编解码软件工程师 [SW] 深度学习算法工程师 [SW] 深度学习推理框架软件工程师 [SW] 资深软件架构工程师 [IP] AI芯片设计工程师 [IP] DDR专家 [IP] C-Model工程师 [IP] PCIe 专家 [FE] SOC flow Engineer [FE] SOC Low Power Design Engineer [FE] Staff STA Engineer [DV] 设计验证工程师 [DV] Formal验证工程师 [DV] PCIe设计验证工程师 [DV] DDR设计验证工程师 [PD] (资深)物理设计工程师 [PV] System Validation Engineer [PV] System Validation Lead 资深系统架构师

[PD] 芯片后端设计工程师 – PR

岗位职责:

1.    模块级的netlistGDS的后端物理实现,包括floorplan,  placement, CTS , routing

2.    解决模块 timing, congestion, 以及IR/EM等问题

3.    负责模块的时序收敛及signoff工作

4.    负责模块的物理验证工作,包含DRCANTLVSERCIREMESD

任职要求:

1.    本科及以上学历,电子工程,微电子,计算机,通信等相关专业;

2.    三年以上芯片后端实现相关工作经验;

3.    熟悉半导体基本知识、原理,以及数字后端的基本知识;

4.    熟练使用ICC/Innovus/PT/StarRC/CalibreEDA工具;

5.    熟练使用TclPerlshell等脚本语言;

6.    有16nm及以下项目经验者优先;


[PD] 芯片后端设计工程师 – IR/EM


岗位职责:

1.    负责芯片的IR Drop分析以及优化

2.    负责芯片powersignal EM分析以及提高

3.    负责blocktop levelpower规划


任职要求:

1.    本科及以上学历,电子工程,微电子,计算机,通信等相关专业;

2.    三年以上芯片后端实现相关工作经验;

3.    熟悉半导体基本知识、原理,以及数字后端的基本知识;

4.    熟练使用Redhawk, voltus, ICC2, InnovusEDA工具;

5.    熟练使用TclPerlshell等脚本语言;

产品市场专员

Product Marketing Specialist


职责描述 Responsibilities

作为瀚博半导体的产品市场专员,您将负责数据中心产品的营销与技术文档,提升客户体验。职责包含但不限于:

1.    深入理解客户业务需求,开展市场研究与竞争分析;

2.    整合、撰写产品技术文档与市场材料,方便客户理解、使用与部署瀚博半导体产品;

3.    策划组织产品发布等营销活动,提升产品风格、品牌形象,推进公司战略。

任职要求 Qualifications

1.    本科或以上学历,计算机、电子、通信、工业设计等相关专业;

2.    2年以上电子或软件产品管理、市场营销、市场沟通、客户体验或技术写作经验;

3.    良好的中英文口头与书面技术沟通能力和团队协作精神;

4.    有文案写作或视觉设计经验者优先考虑;

5.    理解半导体芯片、深度学习框架与模型、计算机视觉或视频处理技术者优先考虑;

6.    熟悉人工智能、大数据、互联网等行业客户的应用场景和客户痛点者优先考虑。

客户解决方案架构师

Customer Solution Architect


职责描述 Responsibilities

作为瀚博半导体的客户解决方案架构师(SA),您将负责发展与云数据中心客户的深度技术合作,设计最优解决方案,力助客户赢得业务成功。职责包含但不限于:

1.    深入理解客户业务需求,推动跨部门合作优化关键系统设计,解决客户应用场景的痛点;

2.    提供完整的售前技术支持,确保客户成功评估并部署瀚博半导体产品,完成项目交付;

3.    结合项目经验、客户诉求与行业趋势,协助下一代产品定义,完善行业解决方案,扩大客户群体。

任职要求 Qualifications

1.    本科或以上学历,计算机、电子、通信等相关专业;

2.    5年以上电子或软件技术解决方案、售前或产品研发工作经验;

3.    良好的口头与书面技术沟通能力和团队协作精神,能独立面向客户沟通需求与解决方案;

4.    善于设计与搭建软硬件概念原型(Proof-of-Concepts),能独立完成客户演示;

5.    具备客户现场样品调试和编程解决问题的经验;

6.    熟悉半导体芯片(GPU, FPGA, ASIC)、深度学习框架与模型、计算机视觉或视频编解码技术者优先考虑;

7.    了解云架构、服务器硬件与软件,了解性能优化相关技术者优先考虑;

8.    熟悉人工智能、大数据、互联网等行业客户的应用场景和客户痛点者优先考虑;

9.    具备复杂项目管理经验者优先考虑。

[SW] AI编译器架构师


Job description:

1. 与IP/SOC设计团队合作进行自研AI芯片的SW/FW/HW协同设计及验证;

2. 对自研AI芯片编程模型进行抽象以便于软件开发。


Minimum Requirements:

1. 熟悉C/C++;

2. 熟悉CUDA/OpenCL者尤佳;

3. 熟悉计算机系统体系结构者尤佳;

4. 熟悉主流深度学习网络模型者尤佳;

5. 熟悉XLA/TVM/Glow/OpenVINO/TensorRT等AI编译器者尤佳;

6. 熟悉LLVM/GCC等编译器者尤佳。

[SW] DSP软件开发工程师

Job description:

1、  DSP 固件开发;

2、  DSP 视觉算法软件开发;

3、  DSP 软件指令、算法优化;

4、  为客户研发提供底层软件支持。

Minimum Requirements:

1、  计算机、电子、通信等专业本科及以上学历;

2、  3年以上DSP软件开发经验,至少对一种DSP 硬件架构、运行机制理解深刻;

3、  具有很强的C/C++编程能力,具备DSP汇编语言编程能力;

4、  具有AI 芯片软件开发经验、各种AI网络常用算子实现的工作经验尤佳;

5、  有半导体公司核心BSP开发团队工作经验者尤佳。

[SW] MCU 固件开发工程师

职位描述:

负责以下一项或全部工作:

1、  MCU 固件开发;

2、  基于芯片bare metal环境下的功能验证开发及调试;

3、  芯片IP驱动开发;

4、  为客户研发提供底层软件支持。

职位要求:

1、  计算机、电子、通信等专业本科及以上学历;

2、  对MCU 硬件架构理解深刻、具备bare metal驱动开发经验;

3、  具有很强的C/C++编程能力,具备一定的汇编语言编程能力;

4、  具有AI 芯片软件开发经验、各种AI网络常用算子实现的工作经验尤佳;

5、  有半导体公司核心BSP开发团队工作经验者尤佳;

6、  有DDR、PCIE、ethernet、SD、video codec、power 其中一种或多种驱动开发经验者尤佳

[SW] 软件工具开发工程师


岗位职责:

1. 开发AI加速器芯片的各主要模块的tracer/profiler/debugger

2. 开发AI加速器芯片SDK/IDE

3. 对AI加速器芯片进行性能/能效分析和优化


任职资格:

1. 掌握应用程序开发技术

2. 掌握至少一种应用程序开发语言(C/C++/Python/Java/C#)

3. 有较强的分析问题和解决问题的能力,具备较强的沟通能力和独立工作能力

[SW] 视频编解码软件工程师


Job description:

-H264/HEVC等视频编码器的驱动及中间层软件;

-编写与所开发代码配套的流程图,设计文档等;


Minimum Requirements:

-熟悉C/C++编程

-熟悉Linux环境下驱动开发

-对视频编解码的原理和码流格式有一定了解;

-有视频相关的驱动/中间件/应用层代码编写/调试经验

[SW] 深度学习算法工程师


Job description:

研究/分析主流AI模型特点,协助软件和硬件设计;

使用tensorflow/pytorch/mxnet/caffe之一实现/复现主流AI模型。


Minimum Requirements:

1、熟悉C/C++;

2、熟悉Python;

3、熟悉CUDA者尤佳;

4、熟悉AI算子实现者尤佳。

职责描述:
-针对深度学习推理的编程框架的设计与实现;
-编写与所开发代码配套的流程图,设计文档等;


任职要求:
-熟悉C/C++编程
-熟悉Linux环境下软件开发
-对主流CNN/RNN/BERT等有一定了解;
-有深度学习系统的部署经验

[SW] 资深软件架构工程师


Job description:

1 、作为资深软件结构工程师,参与公司的整体软件架构设计并且和多个软件,硬件和架构部门紧密合作

2、 参与和领导软件层面的产品的定义,开发,量产和客户支持


Minimum Requirements:

1、计算机、电子、通信等专业硕士及以上学历;

2、有半导体公司核心软件架构团队工作经验者尤佳;

3、12年以上的基于X86、ARM 平台的软件架构和开发经验;

4、熟悉嵌入式开发,有ARM Cortex-A 平台开发经验;

5、具有AI 芯片软件开发经验;

6、熟悉H264/H265/MPEG等音视频编解码格式和算法;

7、DSP软件开发经验,至少对一种DSP 硬件架构、运行机制理解深刻;

8、具有很强的C/C++编程能力,具备一定的汇编语言编程能力;

9、有很强的软件架构大局观已经上面多项具体软件方面的多年业界经验;

10、有很强的沟通和协作能力,和良好的团队合作精神;

11、有很强的分析和解决问题能力。

[IP] AI芯片设计工程师

AI Designer


Job Description:
1.As AI block owner, participate AI system related blocks design and integration work.
2.Prepare block architecture and design specification, RTL coding and implement the design.
3.Estimate and optimize AI network performance, guide physical design.

Requirements:
1. Minimum of 3 years of AI related design experience is required.

2.Technical knowledge with AI network, hardware structure, specification, design and implementation.
3.ASIC design frontend experience of synthesis, Lint and CDC is required.
4.Hardware debug and troubleshooting skills are highly desirable.
5.Good English read, write and communication skill.

[IP] DDR专家

DDR Expert


Job Description:

1. As DDR subsystem architect, co-work with SoC Architect on SoC chip definition;

2. Estimate DDR subsystem performance in design early stage and guide IP/NoC to optimize DDR traffic.

3. Analysis the DDR traffic performance in SoC scenario and Guide MC controller/PHY tuning for performance improvement.

4. Take part in DDR subsystem silicon bring up and performance optimization.

 

Requirements:

1. A minimum of 8 years of DDR/LPDDR related design experience is required.

2. Technical knowledge with DDR Protocols, Specification, Design, Verification, and Implementation.

3. ASIC design experience with Simulation/Verification and RTL Synthesis is required

4. Relevant experience in DDR PI/SI design is a big plus.

5. Hardware debug and troubleshooting skills are highly desirable

6. Good communication skill.

 


[IP] C-Model工程师

职责

1、负责自研AI芯片算法和功能行为的设计分析及其CModel开发。
2
、负责CMODEL和驱动的协同开发,以辅助硬件设计验证。
3
、跟RTL团队合作,进行交叉验证。
1. Design and analyze algorithms and features of AI chip, and develop corresponding behavior and performance model.
2. Cowork with driver team to verify function and performance of new algorithms and features based on CModel.
3. Co-work with RTL team, cross-verify the CModel and RTL.
要求
1.
计算机相关专业,本科及以上学历, 3年以上相关工作经验
2.
熟悉计算机系统体系和架构
3.
CPU/DSP/GPU架构设计和它们模拟器开发和性能分析经验者优先考虑。
4.
熟练掌握C/C++、汇编、等基本技能;
5.
有独立工作的能力,同时具有很好的团队协作能力与沟通能力。对技术执着,追求卓越品质。
1. Bachelor and above for CS/EE or related majors. 3+ working experience.
2. Familiar with compute system architecture
3. Familiar with CPU/DSP/GPU
s architecture design, and CMODELs development as well as the performance profiling is better.
4. Excellent on C/C++ and familiar with ASM.


[IP] PCIe 专家

PCIe Expert


Job Description:
As PCIe owner, take charge of PCIe system related design and integration work.
Prepare PCIe architecture and design specification, RTL coding and implement the design.
Estimate PCIe performance in design early stage and guide soc network design.
Optimize PCIe performance from bandwidth, latency, power, and guide physical design.

Requirements:
Minimum of 5 years of PCIe related design experience is required.
Technical knowledge with PCIe protocols, specification, design, verification, and implementation.
Experience on AMBA(AXI/AHB/APB) bus protocol.
Experience on PCIe bring up is a strong plus.
ASIC design frontend experience of synthesis, lint and cdc is required.
Hardware debug and troubleshooting skills are highly desirable.
Good English read, write and communication skill.

Senior Staff SOC flow Engineer


Responsibilities

1. Develop and maintain methodology and flows related to Synthesis/Timing Analysis/Formality Check/Lint/CDC etc.

2. Resolve flow and EDA tool issues to support project execution.

3. Integrate and validate new EDA tools in the flows.

4. Participate in SoC/IP level synthesis/ timing analysis / formality check / CDC check etc.


Requirements

1.      MSEE with > 7year+ experience of digital design experience;

2.      Should have proficiency in flow development and scripting.

3.      Be proficient at scripts language like TCL / Perl / shell / Python / makefile or others

4.      Familiar with EDA tools such as DC/Formality/primetime/spyglass etc.

5.      Must have good communication and analytical thinking skills.

6.      Proficient in English language and application


Professional Skills

1.      Excellent communication and organizational skills                                   

2.      High level of analytical thinking                                         

3.      Quality and risk management skills                                   


Special Requirements:

1.      Customer Orientation, People Orientation, Achievement Orientation

2.      Leadership, Impact and Self confidence

Senior Staff SOC Low Power Design Engineer

Job Objective: SOC power estimation and optimization


Responsibility

 1. Work closely with software, hardware and IP team to plan the chip clock architecture and low power proposal

 2. Power estimation and optmization before chip TO, power breakdown and analysis after chip back

 3. Low power features development and verification

 4. Co-work with design and verification teams on power test plan

 5. Define power optimization solution/methodology/flow and drive them into the design


Requirements

1.      MS with 5+ years' or BS with 8+ years' experience in ASIC design

2.      Experienced in power analysis and optimization

3.      Experienced in low power design

4.      Experience with power tools PowerArtist, PowePro, PTPX

5.      Familiar with scripting languages like Perl, Python, Makefile, etc

6.      Good understanding of the synthesis and backend flows 

7.      Strong problem solving, teamwork and communication skills

8.      Proficient in English language and application


Professional Skills: 

1.      Excellent communication and organizational skills                                          

2.      High level of analytical thinking                                       

3.      Quality and risk management skills                                         


Special Requirements:

1.      Customer Orientation, People Orientation, Achievement Orientation

2.      Leadership, Impact and Self confidence

[FE] Staff STA Engineer


Responsibilities

1. Block and full-chip level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation).

2. Develop and maintain methodology and flows related to timing verification and closure.

3. Generate block and full chip level timing constraints.

4. Resolve complex timing issues for major building blocks of complex SoCs.

 

Requirements

1. 3/5+ years' experience in ASIC timing constraint generation and timing closure.

2. Thorough knowledge of the ASIC design timing closure flow and methodology.

3. Experience in STA tools and flows.

4. Knowledge of timing corners/modes, process variations and signal integrity related issues.

5. Hands on experience in timing/SDC constraints generation and management.

6. Proficient in scripting languages (TCL and Perl)

7. Strong ability in constraint analysis and debug, using industry standard tools such as Synopsys GCA

8. Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and bist testing

9. Proficient in English language and application

 

Professional Skills

• Excellent communication and organizational skills                                        

• High level of analytical thinking                                     

• Quality and risk management skills                                       

 

Special Requirements:

• Customer Orientation, People Orientation, Achievement Orientation

• Leadership, Impact and Self confidence

[DV] 设计验证工程师

MCU/DSP Design Verification Engineer

Job description:

1.Work on MCU/DSP IP/SOC verification in AI machine learning project using SystemVerilog, UVM or C.

2.Coworking with architects and design engineers on the function/performance test plan.

3.Responsible for test cases development and debug.

4.Implement directed and random testcase in UVM/SV/C, as well as checkers and assertions.

5.Doing coverage analysis and bug cleanup in regression.

Minimum Requirements:

1.MS with 2+years or BS with 3+ years experience in MCU/DSP design verification.

2.Deep understanding of MCU or DSP architecture.

3.Experience in C and assembly code programming.

4.Knowledge of UVM, SV, assertions and functional coverage;

5.Strong problem solving and communication skills, team player.

6.Familiar with scripting languages like Perl, Makefile is a big plus.

[DV] Formal验证工程师

Formal Design Verification Engineer

Job description:

1. Work on IP/SOC verification in AI machine learning project using Formal.

2. Work on formal verification including formal property verification, sequential equivalence checking, formal coverage analysis, connectivity checking and other formal verification apps.

3. Coworking with architects and design engineers on the test plan.

4. Responsible for test cases development and debug.

5. Doing coverage analysis and bug cleanup in regression.

Minimum Requirements:

1. MS with 2+years or BS with 3+ years experience in formal verification.

2. Solid understanding of Formal Verification concepts plus hands-on experience verifying and signing-off using formal verification.

3. Experience with formal verification tools: VC Formal, Jasper, Questa Formal.

4. Strong problem solving and communication skills, team player.

5. Familiar with scripting languages like Perl, Makefile is a plus.

[DV] PCIe设计验证工程师

PCIe Design Verification

Job Description:

1.Work on PCIe IP/SOC verification in AI machine learning project using SystemVerilog, UVM or C++.

2.Coworking with architects and design engineers on the function/performance test plan.

3.Responsible for test cases development and debug.

4.Implement directed and random testcase in UVM/SV/C++, as well as checkers and assertions.

5.Doing coverage analysis and bug cleanup in regression.

Minimum Requirements:

1.MS with 2+years or BS with 3+ years experience in PCIe design verification.

2. Deep understanding of PCIe protocol in MAC/Data Link/PHY layers;

3. Knowledge of UVM, SV, assertions and functional coverage;

4.Strong problem solving and communication skills, team player.

5.Familiar with scripting languages like Perl, Makefile is a plus.

[DV] DDR设计验证工程师

DDR Design Verification Engineer

Job description:

1.Work on DDR controller/PHY IP/SOC verification in AI machine learning project using SystemVerilog, UVM.

2.Coworking with architects and design engineers on the function/performance test plan.

3.Responsible for test cases development and debug.

4.Implement directed and random testcase in UVM/SV, as well as checkers and assertions.

5.Doing coverage analysis and bug cleanup in regression.

Minimum Requirements:

1.MS with 2+years or BS with 3+ years experience in DDR design verification.

2. Deep understanding of DDR JEDEC protocol.

3. Knowledge of UVM, SV, assertions and functional coverage;

4.Strong problem solving and communication skills, team player.

5.Familiar with scripting languages like Perl, Makefile is a plus.

[PD] (资深)物理设计工程师

Staff Physical Design Engineer

Job description:

Work with Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron AI chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.

Minimum Requirements:

1.     MSEE with 5+ years or Bachelor with 7+ years of industrial experience in ASIC design

2.     5+ years or more years of experience in physical design of deep submicron digital ASIC chips

3.     Hands on experience in large scale ASIC chip physical design

4.     Knowledgeable in all aspects of deep submicron ASIC design flow

5.     Successfully gone through several complete product development cycles

6.     Demonstrate strong leadership and work well with cross-functional teams

7.     Good listening, writing and speaking English

8.     Good communication skills, strong interpersonal skills and the flexibility

9.     Dedicated, hard working and good team player

10.    Familiar with Back-End (physical design) EDA tools

11.    Familiar with Front-End EDA tools is a plus

12.    Familiar with Unix/Linux environment and good at scripts

System Validation Engineer (SMTS/MTS)

Responsibilities:

·        PCIE/DDR bringup by coworking with IP/DV team.

·        Responsible for functional, electrical test on system board

·        Develop silicon level characterization test plan

·        working with ATE test engineer on the PVT correlation.

·        Enable SLT tests by working with IP/DV team

 

Requirements:

·        5+ years’ experience in silicon debug or validation experience

·        Experience in DDR or PCIE bringup is strongly recommended;

·        Familiar with high-speed circuit test equipment

·        Good script skill will be preferred

·        Experience with ATE test engineer will be a plus

System Validation Lead (PMTS or Sr. Mgr)

Responsibilities

  • Define pre-silicon or post-silicon validation strategy and test plan by coworking with architect, hardware, ASIC and SW teams.
  • Work out the power/performance profiling and product bounding box definition;
  • Be responsible for silicon function bringup, power and thermal measurement & characterization
  • Overseeing silicon validation test coverage and test plan execution schedule
  • Work with SW/Arch team on the performance optimization;

Qualification

  • 10+ years' experience in silicon enablement area
  • Expertise in AI/GPU products bringup will be a big plus.
  • Power/Performance experience will be preferred.
  • Team player will be a must requirement.
  • Good communication skill

资深系统架构师


工作职责:

1. 参与产品和系统的架构设计

2. 理解系统的业务需求,制定系统的整体框架

3. 确定系统边界的划分,系统间交互的实现方式,并对架构实现的可用性、性能指标等进行评估

4. 作为技术专家为项目、产品开发团队提供技术支持,并协助解决系统开发、运行中出现的问题


任职要求:

1.  熟悉云端服务器架构及存储、GPU,CPU,AI加速器,网络等子系统架构

2. 了解大数据、云计算相关架构及组件

3. 了解AI 深度学习相关技术者尤佳

4. 了解流媒体系统者尤佳

5. 有系统厂商(浪潮,联想,华为,戴尔,惠普,新华三等等),系统ODM,Intel/AMD/Nvdia/Xilinx, 或者互联网大厂系统设备经验者尤佳

6,10年以上工作经验 (系统,硬件,和软件设计)

7,本科,硕士或者博士相关专业毕业